`timescale 1ns/1ps

module TB_OH_RXOHCAP;


wire                          GTM_RXOH_RESET;

wire                          MPI_CLOCK;
wire                          MPI_RXOHCAP_START;
wire[10:0]                    MPI_RXOHCAP_ADDR;
wire[63:0]                    MPI_RXOHCAP_RD;

wire                          RXCAP_CLOCK;
wire[63:0]                    RXCAP_DATA;
wire[2:0]                     RXCAP_FRM_FCNT8;
wire[8:0]                     RXCAP_FRM_FCNT270;
wire[3:0]                     RXCAP_FRM_FCNT9;

reg                           tb_reset;
reg                           tb_rxcap_clock;
reg[63:0]                     tb_rxcap_data;
reg[2:0]                      tb_rxcap_frm_fcnt8;
reg[8:0]                      tb_rxcap_frm_fcnt270;
reg[3:0]                      tb_rxcap_frm_fcnt9;

wire                          tb_mpi_clock;
reg                           tb_mpi_rxohcap_start;
reg[10:0]                     tb_mpi_rxohaddr;

initial begin
   tb_reset                    =1'b1;
   tb_rxcap_clock              =1'b0;
   tb_rxcap_data[63:0]         =64'd0;
   tb_rxcap_frm_fcnt8[2:0]     =3'd0;
   tb_rxcap_frm_fcnt270[8:0]   =9'd0;
   tb_rxcap_frm_fcnt9[3:0]     =4'd0;
   tb_mpi_rxohcap_start        =1'b0;
   #200;
   tb_reset                    =1'b0;
   #1000000;
   tb_mpi_rxohcap_start        =1'b1;
end

initial begin
   tb_mpi_rxohaddr[10:0]       =11'd0;
   #1500000;
   tb_mpi_rxohaddr[10:0]       =11'd1;
   #1000;
   tb_mpi_rxohaddr[10:0]       =11'd2;
   #1000;
   tb_mpi_rxohaddr[10:0]       =11'd24;
   #1000;
   tb_mpi_rxohaddr[10:0]       =11'd25;
   #1000;
   tb_mpi_rxohaddr[10:0]       =11'd48;
   #1000;
   tb_mpi_rxohaddr[10:0]       =11'd49;
   #1000;
end

always begin
   #3.2;
   tb_rxcap_clock                 <=!tb_rxcap_clock;
end

always @(posedge tb_rxcap_clock) begin
   tb_rxcap_frm_fcnt8[2:0]        <=tb_rxcap_frm_fcnt8[2:0]+3'd1;
end
always @(posedge tb_rxcap_clock) begin
   if (tb_rxcap_frm_fcnt8[2:0]==3'd7) begin
      if (tb_rxcap_frm_fcnt270[8:0]==9'd269)
         tb_rxcap_frm_fcnt270[8:0]        <=9'd0;
      else
         tb_rxcap_frm_fcnt270[8:0]        <=tb_rxcap_frm_fcnt270[8:0]+9'd1;
   end
end
always @(posedge tb_rxcap_clock) begin
   if (tb_rxcap_frm_fcnt8[2:0]==3'd7 && tb_rxcap_frm_fcnt270[8:0]==9'd269) begin
      if (tb_rxcap_frm_fcnt9[3:0]==4'd8)
         tb_rxcap_frm_fcnt9[3:0]          <=4'd0;
      else
         tb_rxcap_frm_fcnt9[3:0]          <=tb_rxcap_frm_fcnt9[3:0] +4'd1;
   end
end
always @(tb_rxcap_frm_fcnt8 or tb_rxcap_frm_fcnt270 or tb_rxcap_frm_fcnt9) begin
   if (tb_rxcap_frm_fcnt9[3:0]==4'd0 && (tb_rxcap_frm_fcnt270[8:0]==9'd0 || tb_rxcap_frm_fcnt270[8:0]==9'd1 || tb_rxcap_frm_fcnt270[8:0]==9'd2))
      tb_rxcap_data[63:0]                 <= 64'hf6f6f6f6_f6f6f6f6;
   else if (tb_rxcap_frm_fcnt9[3:0]==4'd0 && (tb_rxcap_frm_fcnt270[8:0]==9'd3 || tb_rxcap_frm_fcnt270[8:0]==9'd4 || tb_rxcap_frm_fcnt270[8:0]==9'd5))
      tb_rxcap_data[63:0]                 <= 64'h28282828_28282828;
   else if (tb_rxcap_frm_fcnt9[3:0]==4'd0 && (tb_rxcap_frm_fcnt270[8:0]==9'd6 || tb_rxcap_frm_fcnt270[8:0]==9'd7 || tb_rxcap_frm_fcnt270[8:0]==9'd8))
      tb_rxcap_data[63:0]                 <= 64'h55555555_55555555;
   else if (tb_rxcap_frm_fcnt270[8:0]>=9'd9)
      tb_rxcap_data[63:0]                 <= 64'hffffffff_ffffffff;
   else
      tb_rxcap_data[63:0]                 <= 64'h00000000_00000000;
end

  assign GTM_RXOH_RESET       =tb_reset;
  assign RXCAP_CLOCK          =tb_rxcap_clock;
  assign RXCAP_DATA[63:0]     =tb_rxcap_data[63:0];
  assign RXCAP_FRM_FCNT8[2:0] =tb_rxcap_frm_fcnt8[2:0];
  assign RXCAP_FRM_FCNT270[8:0]    =tb_rxcap_frm_fcnt270[8:0] ;
  assign RXCAP_FRM_FCNT9[3:0]      =tb_rxcap_frm_fcnt9[3:0];

  assign MPI_CLOCK                 =tb_rxcap_clock;
  assign MPI_RXOHCAP_START         =tb_mpi_rxohcap_start;
  assign MPI_RXOHCAP_ADDR[10:0]    =tb_mpi_rxohaddr[10:0];

OH_RXOHCAP                        TU_OH_RXOHCAP(
   .GTM_RXOH_RESET                ( GTM_RXOH_RESET ),

   .MPI_IN_CLOCK                  ( MPI_CLOCK ),
   .MPI_IN_RXOHCAP_START          ( MPI_RXOHCAP_START ),
   .MPI_IN_RXOHCAP_ADDR           ( MPI_RXOHCAP_ADDR[10:0] ),
   .MPI_OUT_RXOHCAP_RD            (),

   .RXCAP_IN_CLOCK                ( RXCAP_CLOCK ),
   .RXCAP_IN_DATA                 ( RXCAP_DATA[63:0] ),
   .RXCAP_IN_FRM_FCNT8            ( RXCAP_FRM_FCNT8[2:0] ),
   .RXCAP_IN_FRM_FCNT270          ( RXCAP_FRM_FCNT270[8:0] ),
   .RXCAP_IN_FRM_FCNT9            ( RXCAP_FRM_FCNT9[3:0] )
   );
endmodule



